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Altera_Forum
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10 years ago

FIFO Outputs all HiZ in RTL Simulation

Hi All, I am still a beginner to FPGAs, but I think I'm making good progress. I am able to simulate my own Verilog code in ModelSim-Altera and everything looks correct. However, when I tr...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

What did you put in the testbench? It looks like there is nothing more than a clock and a reset stuck at 1