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Altera_Forum
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10 years ago

FIFO Outputs all HiZ in RTL Simulation

Hi All, I am still a beginner to FPGAs, but I think I'm making good progress. I am able to simulate my own Verilog code in ModelSim-Altera and everything looks correct. However, when I tr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Right now the test bench IS just a clock signal. I added in a reset to 1 in that screenshot just to try it out. Whether it is 1 or 0, the outputs are still HiZ. I also tried what msj suggested, which was drive reset to 1 for a few clocks, then drive to 0. Still no change.

I have also tried some write signals previously. Here's another screenshot. I think this should write 5 bytes of 8'b10101010 to the FIFO. Is this wrong?