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Altera_Forum
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10 years ago

FIFO Outputs all HiZ in RTL Simulation

Hi All, I am still a beginner to FPGAs, but I think I'm making good progress. I am able to simulate my own Verilog code in ModelSim-Altera and everything looks correct. However, when I tr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I posted a test bench file, but that is awaiting moderation for some reason. In the meantime, I'm not entirely sure how to answer that question msj.

I am opening the Verilog files in a ModelSim project and compiling them there. I am then running the vsim command on the module itself. The module was generated using the Quartus II Megawizard. There is no code of my own, except for the test bench.

I don't think this is a problem with code though. This problem is occurring for any of the generated megafunctions. Even when I try to simulate a PLL megafunction, which takes no inputs but a 50MHz clock, has HiZ outputs. I must be doing something else wrong, but I have no idea what it might be.