Hello, I have DC FIFO I am working with in my design, and the FIFO is constantly showing it is both full and empty at the same time. The FIFO fills up with sampled and analyzed data from an ADC to wait for the microprocessor to come take them, and the processor is looking for the full flag to go high and the empty flag to be low, however the signals are showing that the FIFO is both full and empty at the same time, any ideas what can cause this?

It tests the personality of your design, as it must decide if its empty or full. Wait, I think that's the half-empty and half-full signal. :) Naturally, that shouldn't occur. Do you have the read and write protection circuitry on? They are by default, but if you turn them off you can write when full or read when empty, which can cause the FIFO to wrap-around and do all sorts of weird stuff.

Thanks for the reply! The protection circuitry is on, and I've followed the guidelines on the request signals and clock timing to make sure that data is available when requested. I am using an asynchronous reset signal, not tied to either clock, and my output width is 8 bits while my input width is 16 bits.

I wouldn't expect it to be a problem, but maybe the mixed bit width is causing a problem? Async FIFOs are used in every design and pretty straightforward. That's the one thing you mention that isn't too common. (I would turn on the write side synchronization for coming out of reset, but that would cause a problem at initial startup and not later on). You may want to file an SR for help. SignalTapping the FIFO control signals would be of interest.

And does it lock up? If you have the read/write protection circuitry on, then you can't read or write when it's empty or full, so having both signals on would prevent you from reading or writing. Just curious.

--- Quote Start --- Hello, I have DC FIFO I am working with in my design, and the FIFO is constantly showing it is both full and empty at the same time. The FIFO fills up with sampled and analyzed data from an ADC to wait for the microprocessor to come take them, and the processor is looking for the full flag to go high and the empty flag to be low, however the signals are showing that the FIFO is both full and empty at the same time, any ideas what can cause this? --- Quote End --- either timing failure or wrong observation. How do you observe the flags?

FIFO IP Full and Empty Simultaneously | Altera Community

16 Replies

Altera_Forum
Honored Contributor
11 years ago
It tests the personality of your design, as it must decide if its empty or full. Wait, I think that's the half-empty and half-full signal. :)
Naturally, that shouldn't occur. Do you have the read and write protection circuitry on? They are by default, but if you turn them off you can write when full or read when empty, which can cause the FIFO to wrap-around and do all sorts of weird stuff.
Altera_Forum
Honored Contributor
11 years ago
Thanks for the reply! The protection circuitry is on, and I've followed the guidelines on the request signals and clock timing to make sure that data is available when requested. I am using an asynchronous reset signal, not tied to either clock, and my output width is 8 bits while my input width is 16 bits.
Altera_Forum
Honored Contributor
11 years ago
I wouldn't expect it to be a problem, but maybe the mixed bit width is causing a problem? Async FIFOs are used in every design and pretty straightforward. That's the one thing you mention that isn't too common. (I would turn on the write side synchronization for coming out of reset, but that would cause a problem at initial startup and not later on). You may want to file an SR for help. SignalTapping the FIFO control signals would be of interest.
Altera_Forum
Honored Contributor
11 years ago
And does it lock up? If you have the read/write protection circuitry on, then you can't read or write when it's empty or full, so having both signals on would prevent you from reading or writing. Just curious.
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Hello,

I have DC FIFO I am working with in my design, and the FIFO is constantly showing it is both full and empty at the same time. The FIFO fills up with sampled and analyzed data from an ADC to wait for the microprocessor to come take them, and the processor is looking for the full flag to go high and the empty flag to be low, however the signals are showing that the FIFO is both full and empty at the same time, any ideas what can cause this?
--- Quote End ---

either timing failure or wrong observation. How do you observe the flags?
Altera_Forum
Honored Contributor
11 years ago
I am observing the control signals and flags via SignalTap, and the FIFO does not lock up while running, the FIFO is only accessed for a short portion of the overall system processes, and the flags can both be asserted regardless of where in the cycle the system is at.
Altera_Forum
Honored Contributor
11 years ago
Can you setup the SignalTap trigger to catch the exact moment when they both get asserted? Also, try disabling the internal protection circuitry and control the read/write signals externally to prevent writing to a full and reading from an empty fifo.
Altera_Forum
Honored Contributor
11 years ago
My recommendation would be to simulate your design. I wrote testbenches for the scfifo and dcfifo and posted them in this thread:

http://www.alteraforum.com/forum/showthread.php?t=38988

The code has lots of comments regarding the FIFO setup and my observations, eg., there are pipeline delays between the flags and counters in dual-clock mode.

Cheers,
Dave
Altera_Forum
Honored Contributor
11 years ago
I had (and still have) a problem with Fifos and Quartus on some projects. On 3-4 projects that I currently maintain, there are a few fifos that have the same behaviour that you describe. The usedw signal is correct, but not the full and empty signals. The only workaround that I found was to delete all generated files, including the db and incremental_db folders, and compile the project from the beginning. Then the fifos work as expected.
You could try and see if you have the same results.
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
I had (and still have) a problem with Fifos and Quartus on some projects. On 3-4 projects that I currently maintain, there are a few fifos that have the same behaviour that you describe. The usedw signal is correct, but not the full and empty signals. The only workaround that I found was to delete all generated files, including the db and incremental_db folders, and compile the project from the beginning. Then the fifos work as expected.
You could try and see if you have the same results.
--- Quote End ---

Oh, dear!

I will try this. I have too many trouble with FIFOs. Just a moment ago, a SCFIFO has the full flag set but usedw all zero.

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FIFO IP Full and Empty Simultaneously

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