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Altera_Forum
Honored Contributor
Honored ContributorFIFO IP Full and Empty Simultaneously
Hello, I have DC FIFO I am working with in my design, and the FIFO is constantly showing it is both full and empty at the same time. The FIFO fills up with sampled and analyzed data from an AD...
Altera_ForumHonored Contributor
Honored ContributorCan you setup the SignalTap trigger to catch the exact moment when they both get asserted? Also, try disabling the internal protection circuitry and control the read/write signals externally to prevent writing to a full and reading from an empty fifo.
