Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

FIFO IP Full and Empty Simultaneously

Hello, I have DC FIFO I am working with in my design, and the FIFO is constantly showing it is both full and empty at the same time. The FIFO fills up with sampled and analyzed data from an AD...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I wouldn't expect it to be a problem, but maybe the mixed bit width is causing a problem? Async FIFOs are used in every design and pretty straightforward. That's the one thing you mention that isn't too common. (I would turn on the write side synchronization for coming out of reset, but that would cause a problem at initial startup and not later on). You may want to file an SR for help. SignalTapping the FIFO control signals would be of interest.