Xcelium Simulation using XRUN with Verilog Configurations defining Library Search Order

Does your design contain any Altera IP? If so, could you let us know which IPs are being used?
Additionally, could you share a test case and the steps required to reproduce the issue?
This information will help us investigate the issue and determine the root cause more effectively.
Thanks.

Regards,
Richard Tan

Richard,

No testcase as I cannot export it from our servers. Yes the design uses a lot of Altera IP including SERDES, Platform Designer Interconnect, DDR4 controller and such.  It does NOT use a processor!

I know not having a test case makes your job a little harder.  I would suggest just using the Altera AgileX High Speed Serial Design Example you already provide.  The cell I mentioned above is part of the high speed SERDES.

Yes, I do have the FPGA with a simple test bench wrapper simulating using the xcelium/xcelium_setup.sh. My problem is that this FPGA is part of a larger system which requires the FPGA to compile using XRUN and operate with a Verilog Configuration to determine the library behavior.

I built a flow to allow this for the Arria5 in a past iteration of this design; but that flow is not working with the AgileX design because the base libraries have changed and the compile order is more sensitive than the Arria5 (or we were very lucky).

I don't have a lot more to tell you at this point, it might be possible to export a LOG file from our serves after I remove any of our proprietary IP information. If you think a LOG would be useful, then let me know what log file you want.  I can provide the LOG file from the xcelium/xcelium_setup.sh compile/elaboration.  Or I can provide a LOG file of the XRUN version that is using my created Verilog Configuration. Please let me know if you think either of those will be helpful.

TomT...

Thank you for the additional information. 

I don't know of an officially documented Agilex encrypted library search order for XRUN Verilog configurations, and the fact that it worked for Arria V but fails for Agilex suggests the newer Agilex simulation hierarchy has additional library dependencies. A successful xcelium_setup.sh elaboration log and the failing XRUN config would be useful to compare. 

Since the design elaborates and simulates successfully using the generated xcelium_setup.sh flow, the generated library compilation order and library mappings are likely correct. The issue appears when moving to the XRUN + Verilog configuration flow, which suggests the problem may be related to library binding/resolution during elaboration rather than the IP generation itself.

Given that you cannot export a test case, log files would indeed be helpful. Please provide both:

1. The xcelium/xcelium_setup.sh compile/elaboration log, this will show us the library compile order and elaboration steps that work, which is the baseline we need.

2. The XRUN log using your Verilog Configuration, this will show us exactly where the BILCNF errors occur and which configuration binding is failing.

We mainly need the library compile order, the default liblist you constructed, and the full error context around the BILCNF messages.

A few things to check in the meantime that may help narrow this down:
1. I suspect that the Agilex encrypted libraries (including the SERDES models like ip7521serdes_*) have stricter library dependencies than Arria 10 or Arria V. The xcelium_setup.sh script compiles them in a specific order. Check if your XRUN flow reorders or omits any of those compile steps, the default liblist in your Verilog Configuration may reference a library that was compiled before its dependency, causing BILCNF.
 

2. When you migrating from xmelab to XRUN, the default liblist in your Verilog Configuration needs to list libraries in the same search order that xmelab used. The key question is: are you deriving this order from the -libname arguments in the xcelium_setup.sh elaboration step, or from the compile step? It should come from the elaboration step's library search order.
 

3. You mentioned XRUN is without cds.lib/hdl.var (or empty), the xcelium_setup.sh typically relies on a cds.lib generated during setup. Please confirm whether the Altera libraries themselves were compiled using xcelium_setup.sh (which may have generated a cds.lib internally) or whether you recompiled them entirely under XRUN's -makelib flow. You might needs to extract the library mappings from the generated cds.lib and replicate them in his XRUN command-line flow or Verilog Configuration default liblist.
 

4. The cell ip7521serdes_uxs2t1r1gpd_pipe_msvmodelknobmod seem to be part of the encrypted SERDES simulation model. These models are typically compiled into a library named something like altera_ver, altera_lnsim, or a variant-specific library. If your default liblist does not include the exact library name that this model was compiled into, the configuration binding will fail even if the cell exists.

If you could create a simplified testcase, it definitely could help us understand how the flow works.

Regards,
Richard Tan