Xcelium Simulation using XRUN with Verilog Configurations defining Library Search Order

Richard,

No testcase as I cannot export it from our servers. Yes the design uses a lot of Altera IP including SERDES, Platform Designer Interconnect, DDR4 controller and such.  It does NOT use a processor!

I know not having a test case makes your job a little harder.  I would suggest just using the Altera AgileX High Speed Serial Design Example you already provide.  The cell I mentioned above is part of the high speed SERDES.

Yes, I do have the FPGA with a simple test bench wrapper simulating using the xcelium/xcelium_setup.sh. My problem is that this FPGA is part of a larger system which requires the FPGA to compile using XRUN and operate with a Verilog Configuration to determine the library behavior.

I built a flow to allow this for the Arria5 in a past iteration of this design; but that flow is not working with the AgileX design because the base libraries have changed and the compile order is more sensitive than the Arria5 (or we were very lucky).

I don't have a lot more to tell you at this point, it might be possible to export a LOG file from our serves after I remove any of our proprietary IP information. If you think a LOG would be useful, then let me know what log file you want.  I can provide the LOG file from the xcelium/xcelium_setup.sh compile/elaboration.  Or I can provide a LOG file of the XRUN version that is using my created Verilog Configuration. Please let me know if you think either of those will be helpful.

TomT...