FIFO IP Full and Empty Simultaneously

--- Quote Start ---

Hello,

I have DC FIFO I am working with in my design, and the FIFO is constantly showing it is both full and empty at the same time. The FIFO fills up with sampled and analyzed data from an ADC to wait for the microprocessor to come take them, and the processor is looking for the full flag to go high and the empty flag to be low, however the signals are showing that the FIFO is both full and empty at the same time, any ideas what can cause this?

--- Quote End ---

either timing failure or wrong observation. How do you observe the flags?