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Altera_Forum
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11 years ago

FIFO IP Full and Empty Simultaneously

Hello, I have DC FIFO I am working with in my design, and the FIFO is constantly showing it is both full and empty at the same time. The FIFO fills up with sampled and analyzed data from an AD...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

It tests the personality of your design, as it must decide if its empty or full. Wait, I think that's the half-empty and half-full signal. :)

Naturally, that shouldn't occur. Do you have the read and write protection circuitry on? They are by default, but if you turn them off you can write when full or read when empty, which can cause the FIFO to wrap-around and do all sorts of weird stuff.