Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

FIFO IP Full and Empty Simultaneously

Hello, I have DC FIFO I am working with in my design, and the FIFO is constantly showing it is both full and empty at the same time. The FIFO fills up with sampled and analyzed data from an AD...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I had (and still have) a problem with Fifos and Quartus on some projects. On 3-4 projects that I currently maintain, there are a few fifos that have the same behaviour that you describe. The usedw signal is correct, but not the full and empty signals. The only workaround that I found was to delete all generated files, including the db and incremental_db folders, and compile the project from the beginning. Then the fifos work as expected.

You could try and see if you have the same results.