Forum Discussion
Altera_Forum
Honored Contributor
11 years agoMy recommendation would be to simulate your design. I wrote testbenches for the scfifo and dcfifo and posted them in this thread:
http://www.alteraforum.com/forum/showthread.php?t=38988 The code has lots of comments regarding the FIFO setup and my observations, eg., there are pipeline delays between the flags and counters in dual-clock mode. Cheers, Dave