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Altera_Forum
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12 years ago

FIFO IP Full and Empty Simultaneously

Hello, I have DC FIFO I am working with in my design, and the FIFO is constantly showing it is both full and empty at the same time. The FIFO fills up with sampled and analyzed data from an AD...
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Altera_Forum
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12 years ago

My recommendation would be to simulate your design. I wrote testbenches for the scfifo and dcfifo and posted them in this thread:

http://www.alteraforum.com/forum/showthread.php?t=38988

The code has lots of comments regarding the FIFO setup and my observations, eg., there are pipeline delays between the flags and counters in dual-clock mode.

Cheers,

Dave