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Honored Contributor
Honored ContributorFIFO IP Full and Empty Simultaneously
Hello, I have DC FIFO I am working with in my design, and the FIFO is constantly showing it is both full and empty at the same time. The FIFO fills up with sampled and analyzed data from an AD...
Altera_ForumHonored Contributor
Honored ContributorThanks for the reply! The protection circuitry is on, and I've followed the guidelines on the request signals and clock timing to make sure that data is available when requested. I am using an asynchronous reset signal, not tied to either clock, and my output width is 8 bits while my input width is 16 bits.
