Forum Discussion

aditya_'s avatar
aditya_
Icon for New Contributor rankNew Contributor
10 months ago

Failed to access library 'altera_ver' quartus 23.1

Hello,
I am new to FPGA's and i am trying to learn to work with them. while i was trying to run an rtl simlation on questasim(free ver) i encountered the following in questasim:

# Reading pref.tcl
# // Questa Intel Starter FPGA Edition-64
# // Version 2023.3 win64 Jul 17 2023
# //
# // Copyright 1991-2023 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // QuestaSim and its associated documentation contain trade
# // secrets and commercial or financial information that are the property of
# // Mentor Graphics Corporation and are privileged, confidential,
# // and exempt from disclosure under the Freedom of Information Act,
# // 5 U.S.C. Section 552. Furthermore, this information
# // is prohibited from disclosure under the Trade Secrets Act,
# // 18 U.S.C. Section 1905.
# //
# do inv_run_msim_rtl_verilog.do
# vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
# Questa Intel Starter FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023
# vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
# Copying C:/intelFPGA_lite/23.1std/questa_fse/win64/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Error (suppressible): (vmap-19) Failed to access library 'altera_ver' at "C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver".
# No such file or directory. (errno = ENOENT)
# Error in macro ./inv_run_msim_rtl_verilog.do line 2
# Questa Intel Starter FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023
# vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
# Copying C:/intelFPGA_lite/23.1std/questa_fse/win64/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Error (suppressible): (vmap-19) Failed to access library 'altera_ver' at "C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver".
# No such file or directory. (errno = ENOENT)
# while executing
# "error [FixExecError $msg]"
# (procedure "vmap" line 29)
# invoked from within
# "vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver"

i can not find anything called altera_ver anywhere. i was getting a different error before which was :

C:/IntelFPGA_lite/23.1std/questa_fse/win64/vsim.exe this did not work and after running the quartus # vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -voptargs="+acc" tb_inv.v
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -voptargs=""+acc"" tb_inv.v
# Start time: 12:07:15 on Feb 06,2025
# ** Error (suppressible): (vsim-19) Failed to access library 'tb_inv' at "tb_inv".
# No such file or directory. (errno = ENOENT)
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./inv_run_msim_rtl_verilog.do PAUSED at line 12

now iam stuck here for past few hours can you please help me out. i am just trying to run a simple inverter program

i have already added the quartus and questa directories to path. i tried to recompile the simulation libraries but there was another error there.

Hdl

22 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    10 months ago

    It's not usually a good idea to have your project in the Quartus installation directory.

    But besides that, can you show your code?

    • aditya_'s avatar
      aditya_
      Icon for New Contributor rankNew Contributor
      10 months ago

      module inv(
      input a,
      output y
      );
      assign y= ~a;

      endmodule
      --------------------------------------

      `timescale 1ns/1ps

      module tb_inv;
      reg a;
      wire y;

      inv uut (
      .a(a),
      .y(y)
      );

      // Testbench logic
      initial begin
      a = 0; #10;
      a = 1; #10;

      end
      endmodule

    • aditya_'s avatar
      aditya_
      Icon for New Contributor rankNew Contributor
      10 months ago

      Hi, I'm sorry if i didn't mention but i am actually using the intel Quartus prime lite software version 23.1 std. with the free license for intel Questa. This specifically. the device i am using is the de-10 nano board by terrasic with intel cyclone 5 [5CSEBA6U23I7]. I have attached a screenshot of the questasim window too and the error message in questasim.

      # Reading pref.tcl
      # // Questa Intel Starter FPGA Edition-64
      # // Version 2023.3 win64 Jul 17 2023
      # //
      # // Copyright 1991-2023 Mentor Graphics Corporation
      # // All Rights Reserved.
      # //
      # // QuestaSim and its associated documentation contain trade
      # // secrets and commercial or financial information that are the property of
      # // Mentor Graphics Corporation and are privileged, confidential,
      # // and exempt from disclosure under the Freedom of Information Act,
      # // 5 U.S.C. Section 552. Furthermore, this information
      # // is prohibited from disclosure under the Trade Secrets Act,
      # // 18 U.S.C. Section 1905.
      # //
      # do inv_run_msim_rtl_verilog.do
      # vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
      # Questa Intel Starter FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023
      # vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
      # Copying C:/intelFPGA_lite/23.1std/questa_fse/win64/../modelsim.ini to modelsim.ini
      # Modifying modelsim.ini
      # ** Error (suppressible): (vmap-19) Failed to access library 'altera_ver' at "C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver".
      # No such file or directory. (errno = ENOENT)
      # Error in macro ./inv_run_msim_rtl_verilog.do line 2
      # Questa Intel Starter FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023
      # vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
      # Copying C:/intelFPGA_lite/23.1std/questa_fse/win64/../modelsim.ini to modelsim.ini
      # Modifying modelsim.ini
      # ** Error (suppressible): (vmap-19) Failed to access library 'altera_ver' at "C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver".
      # No such file or directory. (errno = ENOENT)
      # while executing
      # "error [FixExecError $msg]"
      # (procedure "vmap" line 29)
      # invoked from within
      # "vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver"

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    10 months ago

    I can see you are using nativelink where Quartus Pro no longer support, in any case, can you double check the steps in

    https://www.intel.com/content/www/us/en/docs/programmable/683080/23-1/using-nativelink-simulation.html


    Then try the following solutions step by step:


    1. Check if the altera_ver Library Exists

    The error "No such file or directory" means that QuestaSim is trying to map altera_ver, but the directory doesn’t exist.


    Manually verify the directory:

    Open File Explorer and navigate to:

    C:/intelFPGA_lite/projects/P2/verilog_libs/

    Check if the altera_ver folder exists.

    If it's missing, the libraries were not correctly installed or compiled.


    2. Generate the Missing Intel Simulation Libraries

    If altera_ver is missing, you need to generate the required Quartus simulation libraries.

    Follow these steps:

    A. Open the Nativelink script

    Open Quartus Prime Lite 23.1.

    Go to Tools → Tcl Scripts.

    Look for compile_simlib.tcl (this script compiles the simulation libraries).

    B. Run the Simulation Library Compilation

    Open QuestaSim Intel FPGA Starter Edition.

    Navigate to the questa_fse/bin directory in your Intel FPGA installation path:

    cd C:/intelFPGA_lite/23.1std/questa_fse/bin

    Run the following command to compile the libraries:

    vsim -do "do C:/intelFPGA_lite/23.1std/quartus/common/tcl/internal/nativelink/compile_simlib.tcl"

    Select Verilog when prompted.

    Ensure you specify the correct path where the compiled libraries should be stored.


    3. Correct the vmap Command

    Once the libraries are compiled, map them correctly in QuestaSim:


    Delete any incorrect mappings

    vdel -lib altera_ver -all

    Re-map altera_ver correctly:

    vlib C:/intelFPGA_lite/23.1std/questa_fse/verilog_libs/altera_ver

    vmap altera_ver C:/intelFPGA_lite/23.1std/questa_fse/verilog_libs/altera_ver

    Verify the mapping

    vmap

    This should list altera_ver mapped to the correct path.


    4. Check modelsim.ini for Incorrect Paths

    Open the modelsim.ini file inside your project directory (C:/intelFPGA_lite/projects/P2/).

    Look for the [Library] section.

    Ensure it has an entry like:

    altera_ver = C:/intelFPGA_lite/23.1std/questa_fse/verilog_libs/altera_ver

    If the path is incorrect or missing, manually add it.


    5. Restart QuestaSim and Re-run the Simulation

    After doing all the above:


    Restart QuestaSim.

    Run:

    vmap

    to check if altera_ver is now mapped.

    Try running your simulation again.


    • aditya_'s avatar
      aditya_
      Icon for New Contributor rankNew Contributor
      10 months ago

      i tried the steps from the document attached, not similar to my quartus prime lite but i did follow similar steps to compile the test bench from the starting itself and i am not sure which file to add along with it so i have added the screenshot.
      Coming to the steps you provided there was no alter_ver folder in

      C:/intelFPGA_lite/projects/P2/verilog_libs/.

      " A. Open the Nativelink script

      Open Quartus Prime Lite 23.1.

      Go to Tools → Tcl Scripts.

      Look for compile_simlib.tcl (this script compiles the simulation libraries)."

      for thew above steps i could not find any tcl scripts in the tcl script window.
      next I tried is :

      B. Run the Simulation Library Compilation

      Open QuestaSim Intel FPGA Starter Edition.

      Navigate to the questa_fse/bin directory in your Intel FPGA installation path:

      cd C:/intelFPGA_lite/23.1std/questa_fse/bin

      but there was no bin folder in the directory also on searching for "compile_simlib.tcl" there were no results in questa_fse folder
      So, basically none of it worked.
      i tried installing everything again and got the following error which is same as before
      # Reading pref.tcl
      # // Questa Intel Starter FPGA Edition-64
      # // Version 2023.3 win64 Jul 17 2023
      # //
      # // Copyright 1991-2023 Mentor Graphics Corporation
      # // All Rights Reserved.
      # //
      # // QuestaSim and its associated documentation contain trade
      # // secrets and commercial or financial information that are the property of
      # // Mentor Graphics Corporation and are privileged, confidential,
      # // and exempt from disclosure under the Freedom of Information Act,
      # // 5 U.S.C. Section 552. Furthermore, this information
      # // is prohibited from disclosure under the Trade Secrets Act,
      # // 18 U.S.C. Section 1905.
      # //
      # do inv_run_msim_rtl_verilog.do
      # vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
      # Questa Intel Starter FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023
      # vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
      # Copying C:/intelFPGA_lite/23.1std/questa_fse/win64/../modelsim.ini to modelsim.ini
      # Modifying modelsim.ini
      # ** Error (suppressible): (vmap-19) Failed to access library 'altera_ver' at "C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver".
      # No such file or directory. (errno = ENOENT)
      # Error in macro ./inv_run_msim_rtl_verilog.do line 2
      # Questa Intel Starter FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023
      # vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
      # Copying C:/intelFPGA_lite/23.1std/questa_fse/win64/../modelsim.ini to modelsim.ini
      # Modifying modelsim.ini
      # ** Error (suppressible): (vmap-19) Failed to access library 'altera_ver' at "C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver".
      # No such file or directory. (errno = ENOENT)
      # while executing
      # "error [FixExecError $msg]"
      # (procedure "vmap" line 29)
      # invoked from within
      # "vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver"




  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    10 months ago

    In that case, can you send over your design.qar files?


    Also, what is the OS that you were using?


    • aditya_'s avatar
      aditya_
      Icon for New Contributor rankNew Contributor
      10 months ago

      i am using windows 11. the files generated by quartus are .qpf. qsf & .qws an the other files cant find any .qar

      i have attached screenshots of 2 projects both have a different issue.
      module inv has the missing library issue
      module mux1 has the following error:
      # //
      # do mux1_run_msim_rtl_verilog.do
      # if {[file exists rtl_work]} {
      # vdel -lib rtl_work -all
      # }
      # vlib rtl_work
      # vmap work rtl_work
      # Questa Intel Starter FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023
      # vmap work rtl_work
      # Copying C:/intelFPGA_lite/23.1std/questa_fse/win64/../modelsim.ini to modelsim.ini
      # Modifying modelsim.ini
      #
      # vlog -vlog01compat -work work +incdir+C:/Users/KANAADA\ NMIT\ 2/Desktop/proj\ questa/projects/p1 {C:/Users/KANAADA NMIT 2/Desktop/proj questa/projects/p1/mux1.v}
      # Questa Intel Starter FPGA Edition-64 vlog 2023.3 Compiler 2023.07 Jul 17 2023
      # Start time: 10:29:46 on Feb 20,2025
      # vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/KANAADA NMIT 2/Desktop/proj questa/projects/p1" C:/Users/KANAADA NMIT 2/Desktop/proj questa/projects/p1/mux1.v
      # -- Compiling module mux1
      #
      # Top level modules:
      # mux1
      # End time: 10:29:46 on Feb 20,2025, Elapsed time: 0:00:00
      # Errors: 0, Warnings: 0
      #
      # vlog -vlog01compat -work work +incdir+C:/Users/KANAADA\ NMIT\ 2/Desktop/proj\ questa/projects/p1 {C:/Users/KANAADA NMIT 2/Desktop/proj questa/projects/p1/mux1_tb.v}
      # Questa Intel Starter FPGA Edition-64 vlog 2023.3 Compiler 2023.07 Jul 17 2023
      # Start time: 10:29:46 on Feb 20,2025
      # vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/KANAADA NMIT 2/Desktop/proj questa/projects/p1" C:/Users/KANAADA NMIT 2/Desktop/proj questa/projects/p1/mux1_tb.v
      # -- Compiling module mux1_tb
      #
      # Top level modules:
      # mux1_tb
      # End time: 10:29:46 on Feb 20,2025, Elapsed time: 0:00:00
      # Errors: 0, Warnings: 0
      #
      # vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -voptargs="+acc" mux1_tb.v
      # vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -voptargs=""+acc"" mux1_tb.v
      # Start time: 10:29:46 on Feb 20,2025
      # ** Error (suppressible): (vsim-19) Failed to access library 'mux1_tb' at "mux1_tb".
      # No such file or directory. (errno = ENOENT)
      # Error loading design
      # Error: Error loading design
      # Pausing macro execution
      # MACRO ./mux1_run_msim_rtl_verilog.do PAUSED at line 12


      this is relevant because i used to get this same error in the module inv also but after a while it changes to the other error somehow.

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    10 months ago

    You can share the .qar project by archiving the project (Project > Archive Project).


    I recommend going through the NativeLink simulation flow, using the example design provided in the user guide below.

    The NativeLink feature helps automatically compile your design, Altera IP, simulation model libraries, and testbench.

    https://www.intel.com/content/www/us/en/docs/programmable/703090/21-1/simulation-quick-start.html


    Once you can simulate the example design, try using the same flow with your current design.


    Additionally, as Strell mentioned, try moving your project directory out of the C drive, as you might encounter permission errors when reading/writing files.


    Regards,

    Richard Tan


    • aditya_'s avatar
      aditya_
      Icon for New Contributor rankNew Contributor
      9 months ago

      Hi,
      Sorry just got to work after long. PFA requested files. I have attached files of the 2 projects that were showing the errors above.
      Device i am using:

      5CSEBA6U23I7


      Thank you for the replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    9 months ago

    Two things that you need to change in your mux1.qar:

    1) In the Nativelink setting where you add the testbench file, when the tool ask for "Test bench name" and "Top level module in test bench", you wrote "mux1_tb.v". Instead you should write "mux1_tb" without the ".v" at the end. This will solve your current error.

    2) After solving the first error, you will get another simulation error that indicate the mux module can not be instantiate. Go to your mux1_tb.v file, change "mux uut" to mux1 uut".

    Simulation should run after implement all the changes.

    Regards,

    Richard Tan

    • aditya_'s avatar
      aditya_
      Icon for New Contributor rankNew Contributor
      9 months ago

      mux_nativelink_simulation.rpt

      Info: Start Nativelink Simulation process
      Info: NativeLink has detected Verilog design -- Verilog simulation models will be used

      ========= EDA Simulation Settings =====================

      Sim Mode : RTL
      Family : cyclonev
      Quartus root : d:/intel/quartus/bin64/
      Quartus sim root : d:/intel/quartus/eda/sim_lib
      Simulation Tool : questa intel fpga
      Simulation Language : verilog
      Simulation Mode : GUI
      Sim Output File :
      Sim SDF file :
      Sim dir : simulation\questa

      =======================================================

      Info: Starting NativeLink simulation with Questa Intel FPGA software
      Sourced NativeLink script d:/intel/quartus/common/tcl/internal/nativelink/modelsim.tcl
      Info: Spawning Questa Intel FPGA Simulation software
      Info: NativeLink simulation flow was successful

      i got this in the report but the questa sim window did not open. Using a different system with windows10, shifted license to the new system.
      pfa qar files