Failed to access library 'altera_ver' quartus 23.1

Hi, I'm sorry if i didn't mention but i am actually using the intel Quartus prime lite software version 23.1 std. with the free license for intel Questa. This specifically. the device i am using is the de-10 nano board by terrasic with intel cyclone 5 [5CSEBA6U23I7]. I have attached a screenshot of the questasim window too and the error message in questasim.

# Reading pref.tcl
# // Questa Intel Starter FPGA Edition-64
# // Version 2023.3 win64 Jul 17 2023
# //
# // Copyright 1991-2023 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // QuestaSim and its associated documentation contain trade
# // secrets and commercial or financial information that are the property of
# // Mentor Graphics Corporation and are privileged, confidential,
# // and exempt from disclosure under the Freedom of Information Act,
# // 5 U.S.C. Section 552. Furthermore, this information
# // is prohibited from disclosure under the Trade Secrets Act,
# // 18 U.S.C. Section 1905.
# //
# do inv_run_msim_rtl_verilog.do
# vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
# Questa Intel Starter FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023
# vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
# Copying C:/intelFPGA_lite/23.1std/questa_fse/win64/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Error (suppressible): (vmap-19) Failed to access library 'altera_ver' at "C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver".
# No such file or directory. (errno = ENOENT)
# Error in macro ./inv_run_msim_rtl_verilog.do line 2
# Questa Intel Starter FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023
# vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
# Copying C:/intelFPGA_lite/23.1std/questa_fse/win64/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Error (suppressible): (vmap-19) Failed to access library 'altera_ver' at "C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver".
# No such file or directory. (errno = ENOENT)
# while executing
# "error [FixExecError $msg]"
# (procedure "vmap" line 29)
# invoked from within
# "vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver"