Forum Discussion
aditya_
New Contributor
1 year agoFailed to access library 'altera_ver' quartus 23.1
Hello, I am new to FPGA's and i am trying to learn to work with them. while i was trying to run an rtl simlation on questasim(free ver) i encountered the following in questasim: # Reading pref.tcl ...
RichardT_altera
Super Contributor
1 year agoTwo things that you need to change in your mux1.qar:
1) In the Nativelink setting where you add the testbench file, when the tool ask for "Test bench name" and "Top level module in test bench", you wrote "mux1_tb.v". Instead you should write "mux1_tb" without the ".v" at the end. This will solve your current error.
2) After solving the first error, you will get another simulation error that indicate the mux module can not be instantiate. Go to your mux1_tb.v file, change "mux uut" to mux1 uut".
Simulation should run after implement all the changes.
Regards,
Richard Tan