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aditya_'s avatar
aditya_
Icon for New Contributor rankNew Contributor
10 months ago

Failed to access library 'altera_ver' quartus 23.1

Hello, I am new to FPGA's and i am trying to learn to work with them. while i was trying to run an rtl simlation on questasim(free ver) i encountered the following in questasim: # Reading pref.tcl ...
Hdl
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
10 months ago

It's not usually a good idea to have your project in the Quartus installation directory.

But besides that, can you show your code?

aditya_'s avatar
aditya_
Icon for New Contributor rankNew Contributor
10 months ago

module inv(
input a,
output y
);
assign y= ~a;

endmodule
--------------------------------------

`timescale 1ns/1ps

module tb_inv;
reg a;
wire y;

inv uut (
.a(a),
.y(y)
);

// Testbench logic
initial begin
a = 0; #10;
a = 1; #10;

end
endmodule