Forum Discussion
aditya_
New Contributor
New ContributorFailed to access library 'altera_ver' quartus 23.1
Hello, I am new to FPGA's and i am trying to learn to work with them. while i was trying to run an rtl simlation on questasim(free ver) i encountered the following in questasim: # Reading pref.tcl ...
sstrell
Super Contributor
Super ContributorIt's not usually a good idea to have your project in the Quartus installation directory.
But besides that, can you show your code?
aditya_module inv(
input a,
output y
);
assign y= ~a;endmodule
--------------------------------------`timescale 1ns/1ps
module tb_inv;
reg a;
wire y;inv uut (
.a(a),
.y(y)
);// Testbench logic
initial begin
a = 0; #10;
a = 1; #10;
end
endmodule
