Failed to access library 'altera_ver' quartus 23.1

I can see you are using nativelink where Quartus Pro no longer support, in any case, can you double check the steps in

https://www.intel.com/content/www/us/en/docs/programmable/683080/23-1/using-nativelink-simulation.html

Then try the following solutions step by step:

1. Check if the altera_ver Library Exists

The error "No such file or directory" means that QuestaSim is trying to map altera_ver, but the directory doesn’t exist.

Manually verify the directory:

Open File Explorer and navigate to:

C:/intelFPGA_lite/projects/P2/verilog_libs/

Check if the altera_ver folder exists.

If it's missing, the libraries were not correctly installed or compiled.

2. Generate the Missing Intel Simulation Libraries

If altera_ver is missing, you need to generate the required Quartus simulation libraries.

Follow these steps:

A. Open the Nativelink script

Open Quartus Prime Lite 23.1.

Go to Tools → Tcl Scripts.

Look for compile_simlib.tcl (this script compiles the simulation libraries).

B. Run the Simulation Library Compilation

Open QuestaSim Intel FPGA Starter Edition.

Navigate to the questa_fse/bin directory in your Intel FPGA installation path:

cd C:/intelFPGA_lite/23.1std/questa_fse/bin

Run the following command to compile the libraries:

vsim -do "do C:/intelFPGA_lite/23.1std/quartus/common/tcl/internal/nativelink/compile_simlib.tcl"

Select Verilog when prompted.

Ensure you specify the correct path where the compiled libraries should be stored.

3. Correct the vmap Command

Once the libraries are compiled, map them correctly in QuestaSim:

Delete any incorrect mappings

vdel -lib altera_ver -all

Re-map altera_ver correctly:

vlib C:/intelFPGA_lite/23.1std/questa_fse/verilog_libs/altera_ver

vmap altera_ver C:/intelFPGA_lite/23.1std/questa_fse/verilog_libs/altera_ver

Verify the mapping

vmap

This should list altera_ver mapped to the correct path.

4. Check modelsim.ini for Incorrect Paths

Open the modelsim.ini file inside your project directory (C:/intelFPGA_lite/projects/P2/).

Look for the [Library] section.

Ensure it has an entry like:

altera_ver = C:/intelFPGA_lite/23.1std/questa_fse/verilog_libs/altera_ver

If the path is incorrect or missing, manually add it.

5. Restart QuestaSim and Re-run the Simulation

After doing all the above:

Restart QuestaSim.

Run:

vmap

to check if altera_ver is now mapped.

Try running your simulation again.