Failed to access library 'altera_ver' quartus 23.1

i am using windows 11. the files generated by quartus are .qpf. qsf & .qws an the other files cant find any .qar

i have attached screenshots of 2 projects both have a different issue.
module inv has the missing library issue
module mux1 has the following error:
# //
# do mux1_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Questa Intel Starter FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023
# vmap work rtl_work
# Copying C:/intelFPGA_lite/23.1std/questa_fse/win64/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
#
# vlog -vlog01compat -work work +incdir+C:/Users/KANAADA\ NMIT\ 2/Desktop/proj\ questa/projects/p1 {C:/Users/KANAADA NMIT 2/Desktop/proj questa/projects/p1/mux1.v}
# Questa Intel Starter FPGA Edition-64 vlog 2023.3 Compiler 2023.07 Jul 17 2023
# Start time: 10:29:46 on Feb 20,2025
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/KANAADA NMIT 2/Desktop/proj questa/projects/p1" C:/Users/KANAADA NMIT 2/Desktop/proj questa/projects/p1/mux1.v
# -- Compiling module mux1
#
# Top level modules:
# mux1
# End time: 10:29:46 on Feb 20,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
#
# vlog -vlog01compat -work work +incdir+C:/Users/KANAADA\ NMIT\ 2/Desktop/proj\ questa/projects/p1 {C:/Users/KANAADA NMIT 2/Desktop/proj questa/projects/p1/mux1_tb.v}
# Questa Intel Starter FPGA Edition-64 vlog 2023.3 Compiler 2023.07 Jul 17 2023
# Start time: 10:29:46 on Feb 20,2025
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/KANAADA NMIT 2/Desktop/proj questa/projects/p1" C:/Users/KANAADA NMIT 2/Desktop/proj questa/projects/p1/mux1_tb.v
# -- Compiling module mux1_tb
#
# Top level modules:
# mux1_tb
# End time: 10:29:46 on Feb 20,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
#
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -voptargs="+acc" mux1_tb.v
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -voptargs=""+acc"" mux1_tb.v
# Start time: 10:29:46 on Feb 20,2025
# ** Error (suppressible): (vsim-19) Failed to access library 'mux1_tb' at "mux1_tb".
# No such file or directory. (errno = ENOENT)
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./mux1_run_msim_rtl_verilog.do PAUSED at line 12

this is relevant because i used to get this same error in the module inv also but after a while it changes to the other error somehow.