Failed to access library 'altera_ver' quartus 23.1

i tried the steps from the document attached, not similar to my quartus prime lite but i did follow similar steps to compile the test bench from the starting itself and i am not sure which file to add along with it so i have added the screenshot.
Coming to the steps you provided there was no alter_ver folder in

C:/intelFPGA_lite/projects/P2/verilog_libs/.

" A. Open the Nativelink script

Open Quartus Prime Lite 23.1.

Go to Tools → Tcl Scripts.

Look for compile_simlib.tcl (this script compiles the simulation libraries)."

for thew above steps i could not find any tcl scripts in the tcl script window.
next I tried is :

B. Run the Simulation Library Compilation

Open QuestaSim Intel FPGA Starter Edition.

Navigate to the questa_fse/bin directory in your Intel FPGA installation path:

cd C:/intelFPGA_lite/23.1std/questa_fse/bin

but there was no bin folder in the directory also on searching for "compile_simlib.tcl" there were no results in questa_fse folder
So, basically none of it worked.
i tried installing everything again and got the following error which is same as before
# Reading pref.tcl
# // Questa Intel Starter FPGA Edition-64
# // Version 2023.3 win64 Jul 17 2023
# //
# // Copyright 1991-2023 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // QuestaSim and its associated documentation contain trade
# // secrets and commercial or financial information that are the property of
# // Mentor Graphics Corporation and are privileged, confidential,
# // and exempt from disclosure under the Freedom of Information Act,
# // 5 U.S.C. Section 552. Furthermore, this information
# // is prohibited from disclosure under the Trade Secrets Act,
# // 18 U.S.C. Section 1905.
# //
# do inv_run_msim_rtl_verilog.do
# vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
# Questa Intel Starter FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023
# vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
# Copying C:/intelFPGA_lite/23.1std/questa_fse/win64/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Error (suppressible): (vmap-19) Failed to access library 'altera_ver' at "C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver".
# No such file or directory. (errno = ENOENT)
# Error in macro ./inv_run_msim_rtl_verilog.do line 2
# Questa Intel Starter FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023
# vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
# Copying C:/intelFPGA_lite/23.1std/questa_fse/win64/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Error (suppressible): (vmap-19) Failed to access library 'altera_ver' at "C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver".
# No such file or directory. (errno = ENOENT)
# while executing
# "error [FixExecError $msg]"
# (procedure "vmap" line 29)
# invoked from within
# "vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver"