External Memory Interface IP on Agilex.

Having looked at the simulation, it appears there are no transaction on the aMM interface from the TG2. It is not clear from the documentation how to stimulate the TG2 to perform any transactions. It does say it should perform 1 transaction after power-up., and that this could be made infinite by chaging a parameter. That did not seem to work either.

Giving up on the simulation, I looked at the interface on Qsys. There appears to be a 576-bit rd/wr bus and a 29-bit address bus. As the DDR4 I chose is 4Gx72, that suggests a single transfer on 576-bits is 8x72, so the 29-address bits would enable me to get to the whole memory. It is not clear, but there is a 7-bit burst count field, so potentially I could send 128x576bits in a single burst (the max allowed by Avalon). I presume the emif interface would wait for all 128 576-bit words to be loaded into it's buffer before it tried to burst them at the DDR.

One thing which is not clear is why there appears to be no byteenables on the emif interface? As I will be writing an Avalon master I can add them (72 of them) and try to connect the interfaces together in Qsys. I suppose it will either throw an error or work.

Again, it strikes me I am missing some important document somewhere which describes how to use this interface.

Answers on a postcard please.

Have you gone through the user guide? There's a lot to setting up an EMIF:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/external-memory-interfaces-support.html

Hello Sir,

May I know if you're using Example Design or your custom design?

I can see the signals like below from the Example Design.

• tg_ctrl_amm_0_waitrequest;
• [575:0] tg_ctrl_amm_0_readdata;
• tg_ctrl_amm_0_read;
• [32:0] tg_ctrl_amm_0_address;
• [71:0] tg_ctrl_amm_0_byteenable;
• tg_ctrl_amm_0_readdatavalid;
• tg_ctrl_amm_0_write;
• [575:0] tg_ctrl_amm_0_writedata;
• [6:0] tg_ctrl_amm_0_burstcount;

I think those signals are from the traffic generator that interact with the external memory interface.

Please let me know if you need help on creating the Example Design.

I think that by enabling ECC, your data bit will become 64bit + 8bit ECC.

So there will be a total of 72bit.

Thanks,

Adzim

Hi Adzim,

As I mentioned above (11-07-2021) I simulated the example design. The interface signal that I showed were from the EMIF IP I generated in Qsys. My error was that I hadn't enabled the Data Mask option. Apparently this is required to get the byte enables.

Interestingly when I enable Data Masks I can't enable DBI to improve SI (they are mutually exclusive). When I try to create the IP it suggests I should use DBI as it is over 1200MHz clock speed. So that seems to suggest is you run a DDR4 RDIMM at 2666 or 3200 you shouldn't access anything less than 576-bit words at a time. So all byte changes would need to be a read-modify-write. That doesn't sound very efficient.

Next, I was planning on using a MTA36ASF4G72PZ – 32GB external RDIMM as simulated on our Intel development board schematics. This is a dual rank device with 4 DQ pins per DQS group. When I select Data Mask, an error pops up saying 'Data Masks are not supported in x4 modes'. So it looks like for this RDIMM, you cannot access anything less than 576-bits (or 512 if ECC is enabled). At least the questions I had about ECC seem to now be resolved. With ECC enabled, the interface drops down to 512-bits wide, so at least that now makes sense.

What is not clear from the documentation still is the timing of writes to the DDR4. I can write up to 128 512-bit words at a time to the Avalon interface. The question is when do they start to be transferred to the physical memory. Is it only when all 128 words have been written or as soon as each word is written. I suppose I will have to simulate it and find out.

Thanks for your help.

Hi Sir,

Thanks for your reply and feedback the issue.

I'm really appreciate it.

The question is when do they start to be transferred to the physical memory. Is it only when all 128 words have been written or as soon as each word is written.

I think it's will transferred immediately because the operation is required the location for it to store the data.

You can simulate it to find on how your data are been processed.

Thanks,

Adzim

Re my last post, I have found the video "Custom Component Development Using Avalon® and Arm* AMBA* AXI Interfaces" which has answered most of this.

Hi,

Do you have the sample of how I can read from and write to external SDRAM through Linux driver on Agilex 7?

I need to use the SDRAM as temporary storage and also to use the bridge to access to the peripherals, like UART, I2C, SPI.

I guess there are 2 parts here.

Firstly, we need to setup the connection using Quartus platform Designer. From here, we can generate the avalon-mm addresses.

Secondly, we need to write a Linux driver to access to these avalon-mm addresses in order to read and write.

Am I correct to say that?

But I can't find the sample on this project. Could someone please help direct me to the proper sample?

I guess there is a Cyclone V one. But its architecture isn't the same. I can't use the Cyclone V one on Agilex 7.

Please help.

Regards