New Contributor
New ContributorHi Adzim,
As I mentioned above (11-07-2021) I simulated the example design. The interface signal that I showed were from the EMIF IP I generated in Qsys. My error was that I hadn't enabled the Data Mask option. Apparently this is required to get the byte enables.
Interestingly when I enable Data Masks I can't enable DBI to improve SI (they are mutually exclusive). When I try to create the IP it suggests I should use DBI as it is over 1200MHz clock speed. So that seems to suggest is you run a DDR4 RDIMM at 2666 or 3200 you shouldn't access anything less than 576-bit words at a time. So all byte changes would need to be a read-modify-write. That doesn't sound very efficient.
Next, I was planning on using a MTA36ASF4G72PZ – 32GB external RDIMM as simulated on our Intel development board schematics. This is a dual rank device with 4 DQ pins per DQS group. When I select Data Mask, an error pops up saying 'Data Masks are not supported in x4 modes'. So it looks like for this RDIMM, you cannot access anything less than 576-bits (or 512 if ECC is enabled). At least the questions I had about ECC seem to now be resolved. With ECC enabled, the interface drops down to 512-bits wide, so at least that now makes sense.
What is not clear from the documentation still is the timing of writes to the DDR4. I can write up to 128 512-bit words at a time to the Avalon interface. The question is when do they start to be transferred to the physical memory. Is it only when all 128 words have been written or as soon as each word is written. I suppose I will have to simulate it and find out.
Thanks for your help.
New ContributorAnother question arrises regarding access to the EMIF. I have an HPS with Arm in it which wants to load the DDR4 with test data. I then have some custom IP which reads that data out and sends it to a DAC via JESD, while also collecting data from an ADC and writing it to the EMIF.
1) The EMIF only has a single Avalon port (if you ignore the optional configuration port). I presume these 2 interfaces to the EMIF, one from the HPS and one from the Custom IP will need to go via an Avalon bridge to the EMIF. Is this correct?
2) In Qsys, does this happen automatically when I connect them directly together or do I have to add a bridge to the design?
3) Is it possible that HPS can have byte access to the physical DDR while the Custom IP does not. It sounds like that is not possible?
4) Does the bridge convert between the 512-bit wide data buses from the EMIF to the 32/64 bit interface on the HPS. I presume it must do. Can you point me to documentation which explains this please?
5) If say the HPS has a 64-bit interface, then how does writing to the EMIF work? Does the bridge implement some width conversion logic which collects 8 64-bit words before writing? What happens when fewer that 8 words are written?
