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Big_Al's avatar
Big_Al
Icon for New Contributor rankNew Contributor
4 years ago

External Memory Interface IP on Agilex.

Hi, I am new to Quartus Prime Pro. I have instantiated a external memory interface in a Qsys design for an Agilex part. I have also generated the example design and simulated it. Looking through the ...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hello Sir,


May I know if you're using Example Design or your custom design?


I can see the signals like below from the Example Design.

  • tg_ctrl_amm_0_waitrequest;
  • [575:0] tg_ctrl_amm_0_readdata;
  • tg_ctrl_amm_0_read;
  • [32:0] tg_ctrl_amm_0_address;
  • [71:0] tg_ctrl_amm_0_byteenable;
  • tg_ctrl_amm_0_readdatavalid;
  • tg_ctrl_amm_0_write;
  • [575:0] tg_ctrl_amm_0_writedata;
  • [6:0] tg_ctrl_amm_0_burstcount;

I think those signals are from the traffic generator that interact with the external memory interface.

Please let me know if you need help on creating the Example Design.


I think that by enabling ECC, your data bit will become 64bit + 8bit ECC.

So there will be a total of 72bit.


Thanks,

Adzim