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New Contributor

4 years ago

External Memory Interface IP on Agilex.

Hi, I am new to Quartus Prime Pro. I have instantiated a external memory interface in a Qsys design for an Agilex part. I have also generated the example design and simulated it. Looking through the ...

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Super Contributor

4 years ago

Have you gone through the user guide? There's a lot to setting up an EMIF:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/external-memory-interfaces-support.html

Big_Al
New Contributor
4 years ago
Yes, I have been through all the documentation and videos. The user guide seems to concentrate mainly on the phy side, which is all very interesting but what I really want to know more about from a user point of view is the Avalon interface. I could try to work it out from my own test bench, but I can't help but think it is probably documented somewhere, which would save me a lot of time.
- sstrell
  Super Contributor
  4 years ago
  What aspect of Avalon? Avalon in general or like the register map of the EMIF IP? You can learn more about Avalon itself in the spec:
  
  https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf
  - Big_Al
    New Contributor
    4 years ago
    I have read the Avalon specs and have used axi before. My specific issue is as I mentioned above on the 5 Nov. The Avalon interface on the emif is 576 bits wide. There are no byte enables and only 29 address bits. So if I want to write to a Specific byte, how can I do this? I would have thought this might be explained somewhere along with other questions like details on when a burst mode starts. Is it after the last bytes of the last 576 byte word is written?