External Memory Interface IP on Agilex.

Having looked at the simulation, it appears there are no transaction on the aMM interface from the TG2. It is not clear from the documentation how to stimulate the TG2 to perform any transactions. It does say it should perform 1 transaction after power-up., and that this could be made infinite by chaging a parameter. That did not seem to work either.

Giving up on the simulation, I looked at the interface on Qsys. There appears to be a 576-bit rd/wr bus and a 29-bit address bus. As the DDR4 I chose is 4Gx72, that suggests a single transfer on 576-bits is 8x72, so the 29-address bits would enable me to get to the whole memory. It is not clear, but there is a 7-bit burst count field, so potentially I could send 128x576bits in a single burst (the max allowed by Avalon). I presume the emif interface would wait for all 128 576-bit words to be loaded into it's buffer before it tried to burst them at the DDR.

One thing which is not clear is why there appears to be no byteenables on the emif interface? As I will be writing an Avalon master I can add them (72 of them) and try to connect the interfaces together in Qsys. I suppose it will either throw an error or work.

Again, it strikes me I am missing some important document somewhere which describes how to use this interface.

Answers on a postcard please.