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Big_Al
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4 years ago

External Memory Interface IP on Agilex.

Hi, I am new to Quartus Prime Pro. I have instantiated a external memory interface in a Qsys design for an Agilex part. I have also generated the example design and simulated it. Looking through the ...
Big_Al's avatar
Big_Al
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4 years ago
Yes, I have been through all the documentation and videos. The user guide seems to concentrate mainly on the phy side, which is all very interesting but what I really want to know more about from a user point of view is the Avalon interface. I could try to work it out from my own test bench, but I can't help but think it is probably documented somewhere, which would save me a lot of time.
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    Big_Al
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    4 years ago
    I have read the Avalon specs and have used axi before. My specific issue is as I mentioned above on the 5 Nov. The Avalon interface on the emif is 576 bits wide. There are no byte enables and only 29 address bits. So if I want to write to a Specific byte, how can I do this? I would have thought this might be explained somewhere along with other questions like details on when a burst mode starts. Is it after the last bytes of the last 576 byte word is written?
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      Big_Al
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      4 years ago

      Maybe I should be more specific. I have generated an external memory IP module for an Agilex fpga, which interfaces to a 32GB (4Gx72) DIMM. It has the following user Avalon interface (amm):

      Avalon Interface:
      Name Role Width Direction Description
      amm_ready_0 waitrequest_n 1 Output Wait-request is asserted when controller is busy
      amm_read_0 read 1 Input Read request signal
      amm_write_0 write 1 Input Write request signal
      amm_address_0 address 29 Input Address for the read/write request
      amm_readdata_0 readdata 576 Output Read data
      amm_writedata_0 writedata 576 Input Write data
      amm_burstcount_0 burstcount 7 Input Number of transfers in each read/write burst
      amm_readdatavalid_0 readdatavalid 1 Output Indicates whether read data is valid
      So, on the face of it I there is a 29-bit address bus which allows unique access to 0.5G address space. So, I can access the full 32GB memory in increments of 576-bits (= 8x72).
      There appears to be no byte enables, so it would suggest I can only access data in 576-bit resolution. Either that or if I want to modify a byte, it would require a 576-bit read-modify-write operation. This doesn't sound right!
      Avalon clearly supports byte-enables, although in this case I would require 72-byte-enables. That doesn't sound right either.
      So it looks like I am going wrong somewhere?
      Unfortunately, the documentation doesn't discuss this aspect of the emif very much. There are many other aspects to this interface which are conspicuous by their absence from the documentation, which make me think I am missing a document somewhere. I just need a few simply examples of writing to and reading from the amm.
      I have watched the 4 videos on the subject, generated and simulated the example code and read the External Memory Interfaces Intel Agilex™ FPGA IP User Guide. I also read the Avalon specs.
      • Big_Al's avatar
        Big_Al
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        4 years ago

        Once I get the Avalon issue out of the way, the next issue will be the ECC. The user guide allows you to 'enable ECC' and there are ECC status bits, so I assumed the generation and detection is built into the emif. I would therefore have thought that the write interface would be x64 not x72 and that the emif would generate the ECC bits in the 9th byte. On the read side, I would have only expected a x64 input and the status flags to indicate any errors. Clearly this is wrong as there is still a x72 interface in both directions. Maybe this is only so you could if that way inclined, make your own algorithm up and implement it. Unfortunately there is nothing in the user guide to clarify what is included and how it works.

        Again, if you know, please share this with me.