Critical warning about asynchronous clock domains from same PLL

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Hey there,

I have an FPGA design where a part is running at 150MHz and one part is running with 75MHz (both sourced from the same PLL). So, IMHO the clocks should be synchronous.

Of course I need to bring data from one clock domain to another clock domain and I am using a 2FF synchronizer. I already did this also in other designs (eg. MAX10) and AFAIR it worked flawlessly.

Now I have a Cyclone IV-FPGA and during synthesis I get a critical warning D101: Data bits are not synchronized when transferred between asynchronous clock domains...

My SDC-file has the following entries:

set_time_format -unit ns -decimal_places 3
create_clock -name {clk_ext} -period 50.000 -waveform { 0.000 25.000 } 
derive_pll_clocks
derive_clock_uncertainty 

I think everything should work, but it isn't :-/

Has anybody an idea what is going wrong here?

Thank you!

Regards

Mathias

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if clk1 is 150MHz and clk2 is 75MHz and in phase from same PLL then they are related and you don't need synchronisers to cross domains yet you are referring to non related clocks reported so your case is not clear.

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Can you post the clocks report from TimeQuest or the output of write_sdc -expand?

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Here is the output of the write_sdc -expand command:

https://pastebin.com/dhefpn2e

AFAIK the negative max input/output delays are to prevent timing errors regarding the input and output pins (the FPGA runs completely asynchronously to the input and output signals).

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if clk1 is 150MHz and clk2 is 75MHz and in phase from same PLL then they are related and you don't need synchronisers to cross domains yet you are referring to non related clocks reported so your case is not clear.

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Yes, they should be related but I do not know why I still get this warning. In the mean time I checked my design on the FPGA and so far it works without problems (I know, that is not a reliable solution...)

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Yes, they should be related but I do not know why I still get this warning. In the mean time I checked my design on the FPGA and so far it works without problems (I know, that is not a reliable solution...)

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My guess is that the warning are not related to PLL clocks but some other clocks in your design

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My guess is that the warning are not related to PLL clocks but some other clocks in your design

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To my understanding I have no further clocks beside the two clocks from the PLL and my clk from the external crystal (only used for the PLL). In the compilation report under 'Design Assistant - High Violations' I get a lot of messages (see attachment). In my opinion it is definiteley a problem with the two PLL clocks since the source and destinations nodes are related to the PLL clocks.

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My guess is that the warning are not related to PLL clocks but some other clocks in your design

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To my understanding I have only three clocks: One input clock from an external crystal and used only as PLL input and the two output clocks from the PLL. Looking in the Compilation Report under Design Assistant - High Violations I see that the PLL clocks are the source and the destination of the warnings, see attachment.