Critical warning about asynchronous clock domains from same PLL

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My guess is that the warning are not related to PLL clocks but some other clocks in your design

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To my understanding I have only three clocks: One input clock from an external crystal and used only as PLL input and the two output clocks from the PLL. Looking in the Compilation Report under Design Assistant - High Violations I see that the PLL clocks are the source and the destination of the warnings, see attachment.