Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCritical warning about asynchronous clock domains from same PLL
Hey there, I have an FPGA design where a part is running at 150MHz and one part is running with 75MHz (both sourced from the same PLL). So, IMHO the clocks should be synchronous. Of course...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- My guess is that the warning are not related to PLL clocks but some other clocks in your design --- Quote End --- To my understanding I have only three clocks: One input clock from an external crystal and used only as PLL input and the two output clocks from the PLL. Looking in the Compilation Report under Design Assistant - High Violations I see that the PLL clocks are the source and the destination of the warnings, see attachment.
