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Altera_Forum
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8 years ago

Critical warning about asynchronous clock domains from same PLL

Hey there, I have an FPGA design where a part is running at 150MHz and one part is running with 75MHz (both sourced from the same PLL). So, IMHO the clocks should be synchronous. Of course...
Altera_Forum's avatar
Altera_Forum
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8 years ago

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Can you post the clocks report from TimeQuest or the output of write_sdc -expand?

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Here is the output of the write_sdc -expand command:

https://pastebin.com/dhefpn2e

AFAIK the negative max input/output delays are to prevent timing errors regarding the input and output pins (the FPGA runs completely asynchronously to the input and output signals).