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Altera_Forum's avatar
Altera_Forum
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8 years ago

Critical warning about asynchronous clock domains from same PLL

Hey there, I have an FPGA design where a part is running at 150MHz and one part is running with 75MHz (both sourced from the same PLL). So, IMHO the clocks should be synchronous. Of course...
Altera_Forum's avatar
Altera_Forum
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8 years ago

The path name refers to PLL2 then PLL1 and this may give you a clue. Normally all clocks default as related yet your warning is about unrelated clocks. I doubt you have decided on unrelated clocks in your sdc