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Altera_Forum's avatar
Altera_Forum
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8 years ago

Critical warning about asynchronous clock domains from same PLL

Hey there, I have an FPGA design where a part is running at 150MHz and one part is running with 75MHz (both sourced from the same PLL). So, IMHO the clocks should be synchronous. Of course...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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Yes, they should be related but I do not know why I still get this warning. In the mean time I checked my design on the FPGA and so far it works without problems (I know, that is not a reliable solution...)

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My guess is that the warning are not related to PLL clocks but some other clocks in your design