Critical warning about asynchronous clock domains from same PLL

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My guess is that the warning are not related to PLL clocks but some other clocks in your design

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To my understanding I have no further clocks beside the two clocks from the PLL and my clk from the external crystal (only used for the PLL). In the compilation report under 'Design Assistant - High Violations' I get a lot of messages (see attachment). In my opinion it is definiteley a problem with the two PLL clocks since the source and destinations nodes are related to the PLL clocks.