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Altera_Forum
Honored Contributor
Honored ContributorCritical warning about asynchronous clock domains from same PLL
Hey there, I have an FPGA design where a part is running at 150MHz and one part is running with 75MHz (both sourced from the same PLL). So, IMHO the clocks should be synchronous. Of course...
Altera_ForumHonored Contributor
Honored ContributorCan you post the clocks report from TimeQuest or the output of write_sdc -expand?
