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Honored Contributor
Honored ContributorCarry Chain used as delay line - Problems with supllying LUT-s with ones and zeros
I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to propagate through chain and in moment when STOP occurs, propagation is sampled by registers. To do so, all it takes is to set all the bits of the first operand (input a) to ‘1’ and the bits of the second operand to ‘0’ (input b). Code which works fine for me is :
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity DelayLine is generic ( DATA_WIDTH : natural := 20 ); port ( output: out signed ((DATA_WIDTH-1) downto 0); a: in signed ((DATA_WIDTH-1) downto 0); b: in signed ((DATA_WIDTH-1) downto 0); START: in std_logic ); end DelayLine; architecture rtl of DelayLine is SIGNAL reg: signed ((DATA_WIDTH-1) downto 0); SIGNAL buf: signed ((DATA_WIDTH-1) downto 0); SIGNAL STOP: std_logic; SIGNAL I: integer := 0; begin process (START) variable s : signed ((DATA_WIDTH) downto 0); begin s := ('0' & a) + ('0' & b) + ('0' & START); buf<=s((DATA_WIDTH-1) downto 0); if (falling_edge(START)) then output<=buf((DATA_WIDTH-1) downto 0); end if; end process; end rtl; PROBLEM: Currently my only idea how to supply every adder block with two required signals ('1' and '0') is to make another two registers; one register with ones and other with zeros. Such solution is making a lots of problems in my design. My question is it possible to make some more simple circuit which will supply adders with ones and zeros. I have tried with nonsequential registers (All elements forced to high or low state) but then my carry chain gets deformation.
