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Altera_Forum
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10 years ago

Carry Chain used as delay line - Problems with supllying LUT-s with ones and zeros

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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Hi parasole,

I am glad to see somebody with the same problem. Currently I am busy but I will contact you tomorrow, so we can discuss more about this topic !

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Well, hope we will find some solutions for the problems :-)

It is quite strange that so few people are interested on this area, as opposite to the ones who regularly asking why would you need to try low level design or manual placing...