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Honored Contributor
Honored ContributorCarry Chain used as delay line - Problems with supllying LUT-s with ones and zeros
I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Actually, you can assign allocation for each LE®ister. --- Quote End --- Assume it should be possible, would you point out to the right direction? BTW, any thing about your implementation?
