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Altera_Forum
Honored Contributor
10 years agoCarry Chain used as delay line - Problems with supllying LUT-s with ones and zeros
I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_Forum
Honored Contributor
10 years agoIf I understood correctly the way you try to measure... I think you need to perform kind of test-bench, i.e. start signal should be longer then one clock period and stop signal to be triggered only once so than you may save the result until you read it for interpretation. I would suggest to use on ff to trigger start signal by clock so let it be high until you reset it for new measurement. For stop signal probably you may use a ff and &gate which will be locked by ff. again ff reset signal would be used for next measurement. That means every measurement cycle will happen only once at every reset signal...
From my side I did not come to the point of testing, for me this is hobby thus playing only on evenings... nevertheless, I will try to build a test bench in the way I described, however in order to be able to analyze the data I think about simple serial interface for collecting TDC measurements...