Carry Chain used as delay line - Problems with supllying LUT-s with ones and zeros

Got your points, I think there should be another way, however I did not find it too, at list by now.

As I stated due of this problem I turned out to low level design and after playing with LUT mask finally got it synthesized. Most interesting over here is that quartus place by default all the elements in line by using one column, at list right now without any additional components. What I found is the way Quartus feed low level, it creates automatically ground level from one cell and feed low level to all other cells. At the same time high level is feed directly, possible this is due of the fpga architecture at gates level. Any way, you may try to adapt the code for your device, not sure about the differences but assume it should not be a big deal. As a basis for my code I used another one found over here posted by FvM...