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Altera_Forum
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10 years ago

Carry Chain used as delay line - Problems with supllying LUT-s with ones and zeros

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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Thanks! I will investigate mentioned approach with low level primitives. Currently I am sick so my work stays at same place :(, but I will be soon back so I will contact you about progress soon!

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Sorry to hear about, hope noting serious...

I am continue to play with my design and found the same as you mentioned, fitter will place the line nicelly however will mess up if adding other design entities. However logiclock solve the problem right away by assigning a region for delay line only. I left the region origin to be floating so allowing the fitter to select the best origin it think as of current design level.