Carry Chain used as delay line - Problems with supllying LUT-s with ones and zeros

So here is my progress till now. Currently I am trying to exploit fact that Quartus build adders in one column. After that with LogicLoc option I manually place delay line in wanted place. In this first phase everything works fine and I get exactly what i need. Problem starts when I move other components on chip; for some reason in some situations delay line gets deformation after changing position of some elements (Fore example I want that START block is placed at the beginning of line). Second problem is mentioned supply of cells with ones and zeros. Here is my temporary solution which is probably reason why my TDC doesn't work: I have grounded one external pin. With logic gates and and not you can make two variables ; one for state "1" and other for state "0". After that you can put this two variables to input of shift register (One shift register with ones and other with zeros). Because shift registers are fed from external pin compiler thinks that input signal can change and preserves FF's. Shift registers are driven by some random clock and that's what am I worried about because I don't know what will happen in time intervals when shift action comes up and delay line needs to be sampled. One idea is to drive shift register with really slow clock, so timing problems can be moved away.