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Altera_Forum
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10 years ago

Carry Chain used as delay line - Problems with supllying LUT-s with ones and zeros

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Actually as I stated, the region is only assigned to TDC line, quartus (btw 13.0sp1) alight them correctly with entry cell being the first one and correct order for every other cells.

Every thing else you may see around is second latch line and priority decoder, I did adapt the code from another TDC project I found but done for Xilinx, btw quite good source of information:

http://cas.tudelft.nl/fpga_tdc/tdc_basic.html

http://www.ohwr.org/projects/tdc-core/wiki

For testing purpose I had similar idea but phase shift indeed is very good point, I have one ready module thus will try to use it.