Honored ContributorHi, I'm trying to compile the attached source codes.
The NPN & PNP BJTs are in VHDL and the diode code is in verilog. I am using Quartus. Need help debugging. Any help will be appreciated. :confused:
Honored ContributorDid you try some of the online tools available on the web ?
Try searching for something like "verilog-to-vhdl-converter"Honored ContributorActually I'm sure Quartus can compile both languages. My query is why the code shows errors when compiling.
I was asking for debugging help. Thanks.Honored ContributorThe 'electricalsystem' VHDL package is not synthesisable and there are function calls in the verilog without any definition of the function, not to mention the boundless real parameters declared. Quartus won't have any of that.
None of these modules are intended for use in an FPGA. Cheers, AlexHonored ContributorHonored ContributorThat looks to be the same VHDL as you posted in your first post. No. The 'electricalsystem' VHDL package is not synthesisable.
I'm unaware of tools that do what you want. Why on earth are you trying to put a BJT into an FPGA? This code will be to assist with a simulation. Cheers, AlexHonored ContributorHonored ContributorThe FPGA will only solve the logic part of your requirements - the logic only. If you specifically need the characteristics of a BJT then put a BJT down on your board!
You will not get any resources inside the FPGA to do this part of your puzzle. Cheers, AlexHonored ContributorHonored ContributorThis 'exercise' you're trying is not very practical. What's the goal here?
What you're trying to do with the nmos looks clear enough. The pmos should look near identical save the polarity of 'p_Gate'. i.e.case p_Gate is
when '0' | 'L' => p_Out <= p_In;
when '1' | 'H' => p_Out <= 'Z';
when others => p_Out <= 'X';
end case;
Got it thanks. I suppose I have asked a lot of questions without properly explaining what I am working on which is why my approach seems a bit peculiar. I am attempting to implement a logic design from switch level since my architecture is hypothetically on a 3 dimensional scale and defining components on switch level would offer the best control (I believe) of the FPGAs performance. Thanks for the input.
