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That looks to be the same VHDL as you posted in your first post. No. The 'electricalsystem' VHDL package is not synthesisable.
I'm unaware of tools that do what you want.
Why on earth are you trying to put a BJT into an FPGA? This code will be to assist with a simulation.
Cheers,
Alex
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Ok. I get it now. Also I know verilog has pmos and nmos switches which are unidirectional which may serve my purposes. My question now is concerning my need for BJTs. I specifically wanted to use PNP because when the current through the gate is low and current in the collector is high, there is some current flow from the collector that passes through the gate. This characteristic is CRUCIAL for my design. Does the pmos primitives in verilog allow for this and if not, how do I configure the pmos so it does posses this characteristic?
Would you happen to know how to code for this?
Thanks.
Honored Contributor
