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The 'electricalsystem' VHDL package is not synthesisable and there are function calls in the verilog without any definition of the function, not to mention the boundless real parameters declared. Quartus won't have any of that.
None of these modules are intended for use in an FPGA.
Cheers,
Alex
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Hi, thanks for the response. Can the attached jpeg vhdl source code for BJTs be used in FPGA?
Plus is there a tool that you know of that can input VHDL/verilog source code and output the algorithm implemented in equation form?
And a tool to convert VHDL/verilog to python?
Thanks.
Honored Contributor
