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Altera_Forum
Honored Contributor
Honored ContributorBJT Code needs Debugging
Hi, I'm trying to compile the attached source codes. The NPN & PNP BJTs are in VHDL and the diode code is in verilog. I am using Quartus. Need help debugging. Any help will be ap...
Altera_ForumHonored Contributor
Honored ContributorThe 'electricalsystem' VHDL package is not synthesisable and there are function calls in the verilog without any definition of the function, not to mention the boundless real parameters declared. Quartus won't have any of that.
None of these modules are intended for use in an FPGA. Cheers, Alex
