BJT Code needs Debugging

This 'exercise' you're trying is not very practical. What's the goal here?

What you're trying to do with the nmos looks clear enough. The pmos should look near identical save the polarity of 'p_Gate'. i.e.

case p_Gate is
when '0' | 'L' => p_Out <= p_In;
when '1' | 'H' => p_Out <= 'Z';
when others => p_Out <= 'X';
end case;

However, these still can't (or perhaps "shouldn't") be use inside an FPGA - although you could consider using then if you connect 'p_Out' to a bidirectional pin on the FPGA. You should never tri-state signals internal to the FPGA - they're not designed to work in that way.

If you simply want an NMOS or PMOS FET, put one down. Save your FPGA for some logic!

Cheers,

Alex