Honored ContributorHi, I'm trying to compile the attached source codes.
The NPN & PNP BJTs are in VHDL and the diode code is in verilog. I am using Quartus. Need help debugging. Any help will be appreciated. :confused:
Honored ContributorAn FPGA has a specified design - sets of slices with LUTs for the logic and registers. Writing code at the pmos/nmos level is not going to work because it will not map to an FPGA. Even in asic you would usually use an existing library rather than define your own - mainly because they are fully tested.
Your extreme low level approach is not going to work in an FPGA, and is unlikely to work in any ASIC tools either. Your code can be used for simulation and research purposes only...Honored ContributorOk. Thanks. I'll switch to gate level and get in touch in case I encounter issues.
