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Altera_Forum
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14 years ago

ALTDDIO_OUT Clock Timing Constraint Question

I apologize if this is answered elsewhere, but have searched for awhile and have not seen what I think is a definitive answer.

I am working on a source-synchronous design in which I am generating a clock from a PLL, then running that clock and the output data through an ALTDDIO_OUT out of the chip. I've been using document AN433 as a reference. In example 6 of that document, it shows the constraints for the generated clock out of the ALTDDIO_OUT as:

"create_generated_clock -name output_clock -source

[get_pins DDR|ddio_outa[0]|outclk] [get_ports clk_out]"

Now, I have not been able to get that to work (using my names), nor have I been able to find a derive command like you can for derive_pll_clocks. Does anyone know how I find the name of the output node of the ALTDDIO_OUT megafunction to properly constrain the generated clock?

Thanks for your help!

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thank you for the response. That was the way I originally set it up, but could not figure out how to meet timing. Trying to run at 150MHz now (and eventually 200MHz), and the clock skew + data delay was too much.

    For reference, I originally was doing the following without using the ALTDDIO:

    create_generated_clock -source {PLL_150_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -multiply_by 6 -duty_cycle 50.00 -name {PLL_150_inst|altpll_component|auto_generated|pll1|clk[0]} {PLL_150_inst|altpll_component|auto_generated|pll1|clk[0]}

    create_generated_clock -name {SSRAM_CLK} -source [get_pins {PLL_150_inst|altpll_component|auto_generated|pll1|clk[0]}] -master_clock {PLL_150_inst|altpll_component|auto_generated|pll1|clk[0]} [get_ports {SSRAM_CLK}]

    EDIT: I meant to add, after reading AN433, was hoping this would cause the clock and data to launch at near the same time (and if too close, I'd add a phase shift to the outbound clock). Is my reasoning sound?

    Thanks again.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    What's your set_output_delay constraint look like? That's just the clock setup, which looks correct, although I'm curious what the input is. What device/speed grade? Most stuff should run 150MHz ssync pretty easily.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    My delays are just set like:

    set_output_delay -add_delay -max -clock [get_clocks {SSRAM_CLK}] 1.400 [get_ports {ADDR[0]}]

    set_output_delay -add_delay -min -clock [get_clocks {SSRAM_CLK}] -0.400 [get_ports {ADDR[0]}]

    for each signal.

    We are targeting a Cyclone 4 GX. Industrial part, so speed grade 7. I am surprised at the trouble I'm having as well. :/ Perhaps because the eval board we are using is a very large 150 (896 package) and my project is very small, but some of the routing delays are very long - for example, I'm seeing 3.4ns delay to get from the output of a gate to the input of the register.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The delays will be long, but they should really all cancel out quite a bit. Are you driving ADDR[0] with a 90 degree phase-shifted tap of the PLL?

    Also, I am confusing the too, but 150MHz is 300Mbps when DDR, which does get more difficult(150Mbps should be pretty easy).
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    It is only SDR, so just 150Mbps.

    It's odd, I just rebuilt it without using the ALTDDIO (and using the same constraints I showed before), and I fail input setup by nearly 4ns. 2.4ns of that is because of the clock path (why do they become so different?). If I put the ALTDDIOs back in, using the exact same constraints (is that even valid?) I make timing. Looking at the chip planner, it does bounce all over the die. Perhaps I pass with the ALTDDIO because it forces the register near the pin? Do I need to do some floorplanning to get it sane? I haven't had to do that before, so I was hoping to avoid it. :) I've included a screenshot of the failure, for what it is worth.

    I was getting very frustrated with it all when I saw the AN433 document, and thought maybe the ALTDDIO would get rid of all my problems!
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The PLL has a dedicated output, whereby its output tap can go directly out a specific port whereby it does not go through the Global clock tree. If you don't have pins assigned, it will generally use this. It's good if you're creating a clock to drive other devices since it has less jitter, but it's terrible for source-synchronous, since the clock going out has no clock tree while the data does, so they're not aligned at all. This dedicated path doesn't have DDR I/O, so once you instantiate them it then goes back to being a regular I/O.

    Your setup relationship is 6.666ns. I assume the hold relationship is 0ns. If so, that means the fitter needs to add delay, approximately 3.333ns, to "center the clock". Is that what you want? Please take a look at the link I sent earlier. Basically, I would suggest either:

    a) Using two taps of the PLL, one to drive the clock and one for data, and phase-shift the clock one 180 degrees. This will send clock/data in a center-aligned fashion.

    b) Use one tap of PLL to drive clock/data. This is to send them edge-aligned. If you want to do this, I change the timing constraints to say the external device will shift the clock into the middle of the data eye.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I had actually read your paper (well, most of it) prior to posting. I didn't think it would work for me, as the data is bidirectional, and I didn't think I would be able to meet my input timings. Very likely though I'm being an idiot, and perhaps I just need to set it up to see how it would work out. I will try it and see what it says.

    By the way, I have the SSRAM_CLK assigned to a specific pin - and since I am using an Altera eval board (that has an SSRAM on it) the pin is not assigned to the dedicated PLL output. I also get the following warning, which I think confirms it:

    Warning: PLL "PLL_150:PLL_150_inst|altpll:altpll_component|PLL_150_altpll:auto_generated|pll1" output port clk[0] feeds output pin "SSRAM_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

    So it should be using the global clock tree, so still confused as to why I get so much clock delay at times. :confused:

    Thanks again for your time.