ALTDDIO_OUT Clock Timing Constraint Question

My delays are just set like:

set_output_delay -add_delay -max -clock [get_clocks {SSRAM_CLK}] 1.400 [get_ports {ADDR[0]}]

set_output_delay -add_delay -min -clock [get_clocks {SSRAM_CLK}] -0.400 [get_ports {ADDR[0]}]

for each signal.

We are targeting a Cyclone 4 GX. Industrial part, so speed grade 7. I am surprised at the trouble I'm having as well. :/ Perhaps because the eval board we are using is a very large 150 (896 package) and my project is very small, but some of the routing delays are very long - for example, I'm seeing 3.4ns delay to get from the output of a gate to the input of the register.